Principal Hardware Design Engineer
Job no: 496798
Work type: Experienced
Location: Kings Langley, UK
Categories: Audio, Communications, Debugger, Electronic design, Processors, Product development, RF electronics, System on Chip and System Design, Technical Writing, Testing, Project Management
Join a dynamic digital ASIC design team in the development of cutting edge consumer communication IP cores, using the latest tools and techniques. Examples of existing products incorporating our highly runtime programmable and build configurable Radio Processing Unit (RPU) IP are digital radios, flat panel televisions, set top boxes, tablets, and mobile telephones. The current focus of the hardware design team is on Wi-Fi, BT, GNSS and other wireless link standards.
- work within a global team on RTL Design Implementation
- be part of the Power and performance optimisation and analysis of the digital design
- be the technical leader of the ASIC design with VHDL or Verilog and/or verification of the project (including debug, code coverage, regression testing, and mapping to FPGA/emulator, gate simulation, formal equivalence)
- be designing and debugging complex control and data paths, using high speed and low power design techniques and using synthesis
- have knowledge of CPU or/an DSP architectures
- Collaborate with the wider software and hardware teams
Abilities make possibilities
You are a team player with excellent analytical skills and problem-solving ability.
You are self-motivated and driven. You accept ownership of issues and drive progress forward and provide a solution.
- Good knowledge of digital logic and Signal Processing and communication theory domain knowledge
- The ability to grasp new concepts and apply them to solving problems
- Experience of RTL based digital design (FPGA or ASIC development) and strong RTL coding skills (VHDL/Verilog)
- Technical team leadership experience driving architecture definition, design and execution of complex communication systems
- Experience of verification planning and the DV life cycle (Formal verification, Gate level verification)
- Design skills from system specification (Matlab/C) for IP development
- Experience in Requirements gathering and analysis from the System team
- Hands on experience in Digital Design Methodologies and FSM based design, low power design methodologies and data path design
- Strong Expertise in Data/control path design of algorithms and fixed-point arithmetic related work
- Excellent Digital design skills and having a good understanding of timing closure and related methodologies like synthesis and STA and experience of handing multiple clock domain designs.
- Experience of writing documentation for internal and external use
You might also have:
- Expertise with PHY design/implementation/verification of any communication systems/protocols such as 802.11 and other wireless protocols
- Knowledge on Lint, ASIC Synthesis, CDC.
- Experience in analyse/debug issues on FPGA bring up is added advantage.
- Leading/Managing a smaller team would be an added advantage.
- C, Perl, TCL, and UNIX shell scripting
- FPGA and emulator experience
- Grasp of communication systems and processing techniques
We are champions of technology
The people at Imagination enable the tech that’s shaping our world, from virtual reality to smart phones, autonomous vehicles to space probes. it’s their creativity that has enabled Imagination to power world-changing electronic products. Dare to dream big? We’ll encourage you to pursue your dream. We listen, we’re open and we’re honest. Whatever it is you need, you’ll be respected and helped along your way.
Want to join the team?
Just click the ‘Apply now’ button to send in your CV.
Advertised: GMT Standard Time