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Senior Hardware Design Engineer

Job no: 496645
Work type: Experienced
Location: Kings Langley, UK
Categories: System on Chip and System Design

Join a dynamic digital ASIC design team in the development of cutting edge consumer communication IP cores, using the latest tools and techniques. Examples of existing products incorporating our highly runtime programmable and build configurable Radio Processing Unit (RPU) IP are digital radios, flat panel televisions, set top boxes, tablets, and mobile telephones. The current focus of the hardware design team is on increasing supported terrestrial/cable/satellite TV and radio broadcast reception, and Wi-Fi/BT/802.15.4 and other wireless link standards.


Working as a part of a team, you will have some or all of the following responsibilities:

  • RTL Implementation using VHDL
  • Verification (debug, code coverage, regression testing, and mapping to FPGA/emulator, gate simulation, formal equivalence)
  • Power and performance analysis
  • Documentation for internal and external use
  • Liaising with other company wide software and hardware teams
  • Digital ASIC design with VHDL or Verilog
  • Ability to design and debug complex control and data paths
  • High speed and low power design techniques
  • Synthesis experience
  • Able to grasp new concepts and apply them to solving problems
  • C, Perl, TCL, and UNIX shell scripting
  • FPGA and emulator experience
  • Knowledge of CPU/DSP architectures
  • Grasp of communication systems and processing techniques
  • Formal verification
  • Gate level verification

You have:

  • 5+ years’ experience in RTL based digital design (FPGA or ASIC development)
  • Strong Design skills from system specification (Matlab/C) for IP development
  • Should have involved in Requirements gathering and analysis from the System team
  • Strong RTL coding skills (VHDL/Verilog)
  • Hands on experience in Digital Design Methodologies and FSM based design, Low power Design methodologies and data path design.
  • Signal Processing and communication theory domain knowledge
  • Strong Expertise in Data/control path design of algorithms and fixed-point arithmetic related stuff
  • Experience of handing multiple clock domain designs.
  • Excellent Digital design skills and having a good understanding of timing closure and related methodologies like synthesis and STA


You might also have:

  • Expertise with PHY design/implementation/verification of any communication systems/protocols such as 802.11 and other wireless protocols
  • Knowledge on Lint, ASIC Synthesis, CDC.
  • Experience in analyse/debug issues on FPGA bring up is added advantage.
  • Leading/Managing a smaller team would be an added advantage.

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